Amazing New Chip

The Kernel · Post by **The Kernel** » 2003-10-16 11:17pm

http://www.theinquirer.net/?article=12145

I think the pic speaks for itself. What else is there to say but DAMN!!!! If this is the future of on-chip multiprocessing then sign me up!

Anyone care to guess at the transistor count? Got to be north of 10 billion...

phongn · Post by **phongn** » 2003-10-16 11:20pm

Well, it'll be some time until multiple-core chips trickle down to the consumer. even though IBM has been doing it for some time. I think AMD's looking into a dual-core AMD64 varient.

The Kernel · Post by **The Kernel** » 2003-10-16 11:23pm

phongn wrote:Well, it'll be some time until multiple-core chips trickle down to the consumer. even though IBM has been doing it for some time. I think AMD's looking into a dual-core AMD64 varient.

Yep, Intel and AMD are both going to do dual core, then quad core on the desktop starting in about 2005-2006. But I doubt we'll ever see something like this; this thing has to have over 10,000 pins at least! Can you imagine the motherboard complexity?

GrandMasterTerwynn · Post by **GrandMasterTerwynn** » 2003-10-17 12:11am

The Kernel wrote:
phongn wrote:Well, it'll be some time until multiple-core chips trickle down to the consumer. even though IBM has been doing it for some time. I think AMD's looking into a dual-core AMD64 varient.
Yep, Intel and AMD are both going to do dual core, then quad core on the desktop starting in about 2005-2006. But I doubt we'll ever see something like this; this thing has to have over 10,000 pins at least! Can you imagine the motherboard complexity?

Hardly. There are chips with up to four embedded CPU cores employed in various and sundry engineering applications right now. The CPUs tend to be interconnected inside the chip already. And really, multi-core chips are going to be the only way to squeeze more performance out of silicon made from current processes. We're coming pretty close to the physical limit of what we can do with conventional processes.

Post by **Gandalf** » 2003-10-17 04:58am

So can I put this in my PC when it comes out?

Einhander Sn0m4n · Post by **Einhander Sn0m4n** » 2003-10-17 08:00am

But how many FPS can it squirt out on Quake?

Evil Idea: that monster as the CPU and a 3GHz P4 as the GPU. I think we'd need a car radiator and a 2kW PSU to use it effectively tho...

EDIT: That's not a chip, that's the whole fucking potato!!!

Sarevok · Post by **Sarevok** » 2003-10-17 09:02am

I have doubts about on-chip multi-processing. Today multi-threading remains a complex programming technique that only advanced programmers use. Even after three years of working with C++ I do not fully understand how it works. There is so much to know on multi-threading that entire books have been dedicated to the topic.

Also multi-threading can cause memory leaks in some cases. If a program uses the Windows API for multiple threading and at the same times utilizes the C/C++ standard library there will be a small memory leak. To counter this programmers can either avoid using the standard library or use the C++ multi-threading rather than Windows multithreading which avoids memory leaks.

Sarevok · Post by **Sarevok** » 2003-10-17 09:06am

So can I put this in my PC when it comes out?

I guess you will have to wait. This processor probobly uses an instruction set different from the current x86 instruction set that most PCs use. Besides it has four processors put into one with a totaly different architecture. So I think it is safe to say current applications won't run on a computer with this processor.

GrandMasterTerwynn · Post by **GrandMasterTerwynn** » 2003-10-17 11:56am

evilcat4000 wrote:I have doubts about on-chip multi-processing. Today multi-threading remains a complex programming technique that only advanced programmers use. Even after three years of working with C++ I do not fully understand how it works. There is so much to know on multi-threading that entire books have been dedicated to the topic.

Also multi-threading can cause memory leaks in some cases. If a program uses the Windows API for multiple threading and at the same times utilizes the C/C++ standard library there will be a small memory leak. To counter this programmers can either avoid using the standard library or use the C++ multi-threading rather than Windows multithreading which avoids memory leaks.

It is possible to resolve some of this using integrated hardware and some operating system intelligence. Mind you that's something of what one would hope for in a more perfect world. And to be quite honest, since when have memory leaks ever stopped Microsoft? (Windows ME especially, and the earlier Win 9x operating systems immediately come to mind.)

Though for single-core performance, one will have to look at technologies further out on the horizon, such as 3D silicon, or semiconductors made from exotic materials, such as diamond. Though if one wanted to get really funky with current hardware, one could have a soft processor core or two buried in reconfigurable logic. That boosts performance by doing some of the computationally intensive stuff inside parallel hardware units, and being able to change those units on-the-fly to maximize performance.

The Kernel · Post by **The Kernel** » 2003-10-17 03:32pm

Gandalf wrote:So can I put this in my PC when it comes out?

Technically, you could load OSX on this thing and fire away. The POWER5 uses the PowerPC instruction set, same as Apple processors. Of course, you might have to do some drive work, but it is possible at least.

phongn · Post by **phongn** » 2003-10-17 04:15pm

Of course, OS X is probably not designed to scale that high, but it could run with some relatively minimal effort

That chip is almost certainly intended for AIX.

The Kernel · Post by **The Kernel** » 2003-10-17 04:54pm

phongn wrote:Of course, OS X is probably not designed to scale that high, but it could run with some relatively minimal effort That chip is almost certainly intended for AIX.

POWER5 is going to replace the current POWER4's, so we will probably see both AIX and Linux configurations availible.

The Cleric · Post by **The Cleric** » 2003-10-17 05:01pm

Yes, but will the poor app-loaded PC users get to play with it?

phongn · Post by **phongn** » 2003-10-17 05:17pm

Einhander Sn0m4n wrote:Evil Idea: that monster as the CPU and a 3GHz P4 as the GPU. I think we'd need a car radiator and a 2kW PSU to use it effectively tho...

The Pentium IV would be a poor GPU.

phongn · Post by **phongn** » 2003-10-17 05:18pm

The Kernel wrote:
phongn wrote:Of course, OS X is probably not designed to scale that high, but it could run with some relatively minimal effort That chip is almost certainly intended for AIX.
POWER5 is going to replace the current POWER4's, so we will probably see both AIX and Linux configurations availible.

AFAIK, Linux does not scale too well on eight-way SMP or NUMA. I know POWER5 will have Linux support ... just not the huge n-way multiple-core processors.

phongn · Post by **phongn** » 2003-10-17 05:19pm

StormTrooperTR889 wrote:Yes, but will the poor app-loaded PC users get to play with it?

Nope. the POWER series is generally intended for things like number crunching, high-end servers and things like mainframes.

The Kernel · Post by **The Kernel** » 2003-10-17 07:32pm

phongn wrote: AFAIK, Linux does not scale too well on eight-way SMP or NUMA. I know POWER5 will have Linux support ... just not the huge n-way multiple-core processors.

Linux scales fine on big systems, it's just a question of what kind of processing you are doing. If you are going to do a loosely coupled system that deals with independent data sets, then Linux works fine.

Most of the POWER5 systems will probably not be large ccNUMA systems but rather individual tightly bound clusters. This is perfect for running in applications where you have independent threads that still require a great deal of memory and CPU horsepower that an x86 Beowulf cluster couldn't handle, but that you don't need more than a single node per thread.

The Kernel · Post by **The Kernel** » 2003-10-17 07:40pm

phongn wrote: Nope. the POWER series is generally intended for things like number crunching, high-end servers and things like mainframes.

POWER CPU's are NOT used in Mainframes; IBM still uses 360-compatible hardware running MVS for their Mainframes.

Pu-239 · Post by **Pu-239** » 2003-10-17 08:07pm

phongn wrote:
The Kernel wrote:
phongn wrote:Of course, OS X is probably not designed to scale that high, but it could run with some relatively minimal effort That chip is almost certainly intended for AIX.
POWER5 is going to replace the current POWER4's, so we will probably see both AIX and Linux configurations availible.
AFAIK, Linux does not scale too well on eight-way SMP or NUMA. I know POWER5 will have Linux support ... just not the huge n-way multiple-core processors.

I thought this was resolved with kernel 2.6?

phongn · Post by **phongn** » 2003-10-17 08:48pm

The Kernel wrote:POWER CPU's are NOT used in Mainframes; IBM still uses 360-compatible hardware running MVS for their Mainframes.

Gah, sorry, I mixed up mainframes with their big iron for a second.

phongn · Post by **phongn** » 2003-10-17 08:50pm

Pu-239 wrote:I thought this was resolved with kernel 2.6?

Maybe, but we don't have the numbers for that out yet. I doubt that anyone with such big iron would run Linux; they can afford more tested solutions such as AIX.

The Kernel · Post by **The Kernel** » 2003-10-18 02:31am

phongn wrote:
The Kernel wrote:POWER CPU's are NOT used in Mainframes; IBM still uses 360-compatible hardware running MVS for their Mainframes.
Gah, sorry, I mixed up mainframes with their big iron for a second.

It's okay, lots of people forget that "mainframe" actually means a very specific kind of computer that is rarely used anymore except by companies that need a great deal of steady I/O throughput such as credit card transactions. Most people today refer to all big iron as mainframes, even the technically minded people who know better. I just mentioned it because we were talking about IBM machines specifically and I like to show off my knowledge of archaic hardware